1. Field of the Invention
The present invention relates to a dual damascene process, and more particularly, to a dual damascene process that combines low-K materials and Cu.
2. Description of the Prior Art
To satisfy requirements for high integration and high speed in integrated circuits (ICs), especially in a deep sub-micro ( less than 0.18 xcexcm) semiconductor process, a Cu dual damascene process is now becoming a more widely used and a standard process in forming an interconnection line within the inter-metal dielectric layer of low dielectric constant (low k) materials. Since Copper has both a low resistance and a low electromigration resistance, the low k materials are useful in improving the RC delay effect of a metal interconnection.
Please refer to FIG. 1 of a cross-sectional diagram of a semiconductor wafer 10 with a typical dual damascene structure 11. As shown in FIG. 1, the dual damascene structure 11 formed within a dielectric layer 20 is composed of a via 22 and a trench 23. A conductive layer 14 is formed in the dielectric layer 12 beneath the via 22, and a Cu conductive layer 24 fills the trench 23. The Cu conductive layer 24 and the conductive layer 14 are connected by a via plug 22a penetrating through the passivation layer 18 between the dielectric layer 12 and the dielectric layer 20.
To prevent a diffusion of Cu from the dual damascene structure 11 into the adjacent dielectric layer 20, a barrier layer 25 is needed on a surface of the dual damascene structure 11 according to the prior art. Commonly, the barrier layer 25 comprises the following properties: (1) good exclusion of the diffusing atoms, (2) good adhesion to Cu and the dielectric layer, (3) proper resistance ( less than 1000 xcexcxcexa9-cm), and (4) good step coverage. Usually Ti, TiN, TaN, WN, etc. are used to form the barrier layer.
However, failure such as a via open normally occurs in the prior Cu dual damascene process. Cu diffuses from the cracks in the barrier layer 25 into the dielectric layer 20, which results in a disconnection problem between the Cu conductive layer 24 and the conductive layer 14. The situation is worsened when the dielectric layer 20 is composed of a low k material with a high thermal expansion coefficient, such as a SiLK(trademark) or a porous structure material. In a dual damascene process of a SILK(trademark) dielectric layer 20 and a TaN barrier layer 25, the thermal expansion coefficients of the SILK(trademark), Cu and TaN are 60 ppm/xc2x0C., 17 ppm/xc2x0C. and 3 ppm/xc2x0C., respectively. The TaN barrier layer 25 with the least thermal expansion coefficient is subject to a thermal stress produced from the SiLK(trademark) dielectric layer 20, thus producing cracking. As a result, via failure is induced.
It is therefore a primary objective of the present invention to provide a dual damascene process to solve the above-mentioned problems.
In a preferred embodiment of the present invention, the dual damascene process first provides a semiconductor wafer comprising a substrate and a conductive layer positioned on the substrate. A first passivation layer, a first dielectric layer and a second passivation layer are respectively formed on the substrate of the semiconductor wafer. Following that, a first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are respectively formed on the surface of the semiconductor wafer with the second dielectric layer filling the via hole. A second lithography and etching process is then performed to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are respectively formed on the surface of the semiconductor wafer with the metal layer filling the dual damascene structure, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.
The present invention uses a hard dielectric material to form a via hole of the dual damascene structure and uses a low-K material to form a trench of the dual damascene structure. Therefore, the dual damascene structure has enough compression resistance to avoid structure deformation and a via open issue, and also produces a low RC delay effect.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.